Routing is a crucial step in the design of integrated circuits. Routing builds on a preceding step, called placement, which determines the location of each active element of an integrated circuit (IC). Once placement has occurred, then routing, i.e., the process of adding all wires needed to properly connect all of the placed components while obeying all design rules, can occur.
Routers are typically given some pre-existing polygons consisting of pins (also called terminals) on cells, and optionally some pre-existing wiring called pre-routes. Each of these polygons is associated with a net, usually by name or number. The primary task of the router is to create geometries such that all terminals assigned to the same net are connected, no terminals assigned to different nets are connected, and all design rules are obeyed. In addition, to correctly connect the nets, routers are also responsible for ensuring that the design meets timing, has no crosstalk problems, meets any metal density requirements, does not suffer from antenna effects, etc. This long list of often conflicting objectives is what makes chip-level routing extremely difficult.
In chip level routing, the typical process is to route the chip first (i.e., perform an initial routing), insert repeaters (buffers) for wires, i.e., to meet a predefined transition time, and subsequently rip and re-route wires (i.e., perform a second-level routing) to connect various nets with repeaters. Repeater insertion is a technique for reducing the transition time associated with long wire lines in integrated circuits. The technique involves cutting the long wire into two or more short wires and inserting a repeater between each new pair of short wires.
In the initial route, designers often need to topologically control some nets for various reasons. For example, a designer may require routing in a specific way in order to cross or be in proximity with repeater banks for repeater solutions, a bus may need to be routed in a bundle so that timing performance of the bus between different bits is very similar, a multiple fan-out net may require a repeater inserted in a tree structure, and/or a multiple fan-out net may need to be routed in a spine route topology.
In a high performance chip, the number of nets requiring such custom route attention can be significant. Thus, the entire routing process is often time consuming and can easily become the bottleneck of the chip integration process. In some cases, when a chip floor plan is modified at a later stage, all custom routes are re-done.